1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a structure for testing a semiconductor memory device at high speed. More specifically, the invention relates to a structure for rapidly and successively selecting word lines in a semiconductor memory device during a testing operation.
2. Description of the Background Art
FIG. 30 schematically shows a whole structure of a dynamic semiconductor memory device in the prior art. The dynamic semiconductor memory device may be a virtual static random access memory (VSRAM), a pseudo-static random access memory (PSRAM) and a dynamic random access memory (DRAM). FIG. 30 illustrates a structure of the dynamic random access memory as a representative example.
In FIG. 30, a dynamic semiconductor memory device 1 includes a control circuit 6 which receives external control signals /W, /OE, /RAS and /CAS through external control signal input terminals (nodes) 2-5 and generates internal control signals, a memory array 7 having memory cells arranged in a matrix as described later in detail, an address buffer 9 which receives external address signals A0-Ai through an address signal input terminals (nodes) 8 and generates an internal row address signal and an internal column address signal under the control of control circuit 6, an internal address generating circuit 10 which is controlled by control circuit 6 to generate a refresh row address signal for designating a row to be refreshed in a refreshing operation, a multiplexer 11 which is controlled by control circuit 6 to pass selectively the address signals from address buffer 9 and internal address generating circuit 10, and a row decoder 12 which is activated under the control of control circuit 6 to decode the internal row address signal from multiplexer 11 for selecting a row (word line) in memory array 7.
Signal /W applied to external control signal input terminal (node) 2 is a write enable signal instructing a data writing operation. Signal /OE applied to external control signal input terminal (node) 3 is an output enable signal instructing a data output operation. Signal /RAS applied to external control signal input terminal (node) 4 is a row address strobe signal starting internal operation of the semiconductor memory device and determining an active period of the internal operation. When signal /RAS is active, circuits such as row decoder 12 related to the operation of selecting a row in memory array 7 are made active. Signal /CAS applied to external control signal input terminal (node) 5 is a column address strobe signal activating circuits related to selection of a column in memory array 7. Functions of these external control signals will be described later in detail.
Semiconductor memory device 1 further includes a column decoder 13 which is activated under the control of control circuit 6 to decode the internal column address signal applied from address buffer 9 to generate a column select signal for selecting a column in memory array 7, sense amplifiers for sensing and amplifying data of memory cells connected to the selected row in memory array 7, I/O gates responsive to the column select signal applied from column decoder 13 to connect the selected column in memory array 7 to an internal data bus a1, an input buffer 15 which is controlled by control circuit 6 to produce internal write data from external write data DQ0-DQj applied to data I/O terminals 17 for transmission onto internal data bus a1 in a data writing operation, and an output buffer 16 which is controlled by control circuit 6 to produce external read data DQ0-DQj from internal read data read onto internal data busa1 for supplying to data I/O terminal 17 in a data reading operation. In FIG. 30, sense amplifiers and I/O gates are indicated by one block 14. Input buffer 15 is activated to produce the internal write data when both signals /W and /CAS are activated to attain a logical low level. Output buffer 16 is activated in response to activation of output enable signal /OE.
FIG. 31 shows an internal structure of memory array 7 shown in FIG. 30. In FIG. 31, memory array 7 includes a plurality of word lines WL arranged corresponding to respective rows of the memory cells and each connected to memory cells in the corresponding row, and a plurality of bit line pairs BL and /BL arranged corresponding to respective columns of memory cells and each connected to the memory cells in the corresponding column. In FIG. 31, there are representatively shown word lines WL0, WL(l-1), WL1 and WL(l+1) and a pair of bit lines BL and /BL.
Each memory cell is arranged corresponding to a crossing of a bit line pair and a word line. In FIG. 31, there are representatively shown a memory cell MCa arranged corresponding to the crossing of word line WL(l-1) -and bit line /BL, a memory cell MCb arranged corresponding to the crossing of word line WL1 and bit line BL, and a memory cell MCc arranged corresponding to the crossing of word line WL(l+1) and bit line /BL. Each of memory cells MCa-MCc includes a capacitor 23 storing information in the form of electric charges, and an access transistor 22 which is turned on to connect a corresponding bit line (BL or /BL) to capacitor 23 in response to a signal potential on the corresponding word line. Access transistor 22 is formed of an n-channel MOS (insulated gate field-effect) transistor.
Row select signal is transmitted onto a word lines WL (WL0-WL(l+1)) from row decoder 12. One sense amplifier contained in block 14 is arranged corresponding to each bit line pair BL and /BL, and differentially amplifies potentials of the corresponding bit line pair BL and /BL. Operation of the semiconductor memory device shown in FIGS. 30 and 31 will be described below with reference to FIG. 32 which is an operation waveform diagram.
FIG. 32 illustrates an operation waveform during data reading.
When signal /RAS is at a high level of the inactive state, semiconductor memory device 1 is in a standby state. In this state, all the row select signals applied from row decoder 12 are inactive, and the potential of each word line WL is at the low level of the inactive state. Bit lines BL and /BL have been precharged to a predetermined potential, e.g., of Vcc/2 (where Vcc is an operation power supply voltage) by a precharging/equalizing circuit (not shown).
When signal /RAS attains the active state of the low level, a memory cycle starts, and row selecting operation starts. Prior to start of the row selecting operation, the operation of precharging bit lines BL and /BL is stopped, and bit lines BL and /BL are in an electrically floating state at a precharged potential.
Address buffer 9 responds to the control signal applied from control circuit 6 via a control signal path a3 to take in external address signals A0-Ai received via address signal input terminals (nodes) 8 and outputting internal row address signal onto internal address bus a4. Internal address bus a4 in FIG. 30 is shown having a bit width of (i+1). However, if address buffer 9 are adapted to output pairs of complementary address signals, internal address bus a4 has a bit width of 2(i+1). Multiplexer 11 is controlled by control circuit 6 to select and apply the internal address signal applied from address buffer 9 to row decoder 12 in the normal operation mode. Row decoder 12 decodes the applied internal address signal, and generates and transmits the row select signal onto the addressed word line in memory array 7. Thereby, the potential of the selected word line WL rises to the high level.
It is assumed that word line WL1 is selected. In this state, access transistor 22 of memory cell MCb is turned on to connect capacitor 23 to bit line BL. If memory cell MCb has stored data of the high level, the potential of bit line BL slightly rises as shown in FIG. 32. Meanwhile, there is no memory cell connected to bit line /BL, so that bit line /BL maintains the precharged potential. Then, the sense amplifier circuit contained in block 14 is activated to amplify differentially the potentials of bit lines BL and /BL, so that the potential of bit line BL onto which data of the high level is read rises to the operation power supply voltage Vcc level, and bit line /BL is discharged to the low level of the ground potential level.
When signal /CAS is activated to attain the low level, address buffer 9 is controlled by control circuit 6 to take in, as the column address signal, external address signals A0-Ai applied to address signal input terminals (nodes) 8 and produce the internal column address signal for transmission onto internal address bus a4. After the sense amplifier is activated and the potentials of bit lines BL and /BL are fixed, column decoder 13 is activated under the control of control circuit 6 to decode the internal column address signal applied from address buffer 9 and produce the column select signal for outputting. In response to this column select signal, the I/O gates which are contained in block 14 and are provided corresponding to the respective bit line pairs are selectively turned on, and the bit line pairs arranged corresponding to the columns designated by the column select signal are connected to internal data busa1. In the data reading operation, output enable signal /OE is activated to attain the low level, and responsively output buffer 16 is activated under the control of control circuit 6 to produce the external read data from the internal read data onto the internal data busa1 for transmission onto data I/O terminals 17. In the data reading operation, write enable signal /W is maintained at the high level of the inactive state. In the data writing operation, the timing at which the internal write data is transmitted onto internal data busa1 corresponds to the timing at which both signals /W and /CAS are activated.
Word lines WL are arranged in parallel with each other at the same interconnection layer, and are electrically isolated from each other by an insulating film. Therefore, a parasitic capacitance exists between the word lines as shown in FIG. 31. In FIG. 31, there are representatively shown a parasitic capacitance 25b between word lines WL(l-1) and WL1 as well as a parasitic capacitance 25b between word lines WL and WL(l+1). Such parasitic capacitances exist not only between the adjacent word lines but also between word lines remote from each other. Bit line pairs BL and /BL and word lines WL are formed at different interconnection layers in directions crossing with each other. Therefore, parasitic capacitances exist at portions crossing each other with an interlayer insulating film therebetween. In FIG. 31, there is representatively shown a parasitic capacitance 26 between bit line BL and word line WL(l-1). Operational effect of parasitic capacitances 25a, 25b and 26 will now be described below.
FIG. 33 shows a distribution of parasitic capacitances between word lines and between word lines and bit lines more in detail. In FIG. 33, there are shown two word lines WLa and WLb and a pair of bit lines BL and /BL. Memory cell MCd is arranged corresponding to the crossing of bit line BL and word line WLa, and memory cell MCe is arranged corresponding to the crossing of bit line /BL and word line WL. A predetermined reference voltage (generally, Vcc/2) Vcp is applied to the electrode of capacitor 23. A parasitic capacitance 25c exists between word lines WLa and WLb, a parasitic capacitance 25d exists between word line WLa and another word line (not shown), and a parasitic capacitance 25e exists between word line WLb and another word line (not shown). A parasitic capacitance 26a exists between word line WLa and bit line BL, a parasitic capacitance 26b exists between bit line BL and word line WLb, and a parasitic capacitance 26d exists between bit line /BL and word line WLb.
The sense amplifier circuit provided corresponding to each bit line pair includes a P-sense amplifier 27 which is activated in response to a sense amplifier activating signal .phi.SP to charge one at a higher potential of bit lines BL and /BL to the operation power supply voltage level, and an N-sense amplifier 28 which is activated in response to a sense amplifier activating signal .phi.SN to discharge the other at a lower potential of bit lines BL and /BL to the ground potential level.
Action of the parasitic capacitances shown in FIG. 33 will be described below with reference to an operation waveform diagram of FIG. 34. FIG. 34 illustrates the operation in the case where word line WLa is selected and memory cell MCd has stored data of the high level (Vcc level).
When word line WLa is selected, its potential rises. The rise of potential of selected word line WLa is transmitted onto word line WLb owing to capacitive coupling by parasitic capacitance 25c, so that the potential of word line WLb slightly rises. In FIG. 34, the rise of potential of nonselected word line WLb caused by this capacitive coupling is shown causing ringing (the ringing occurs by the fact that a word driver included in row decoder 12 and provided corresponding to each word line maintains the potential level of the nonselected word line at the ground voltage level, i.e., low level).
When the potential of selected word line WLa rises, access transistor 22 in memory cell MCd is turned on, so that electric charges accumulated in capacitor 23 are transmitted onto bit line BL to raise the potential of bit line BL by .DELTA.R. When read voltage .DELTA.R on bit line BL increases to a sufficiently large value, sense amplifier activating signals .phi.SN and .phi.SP are activated. In general, sense amplifier activating signal .phi.SN is first activated, so that N-sense amplifier 28 operates, and the potential of bit line /BL which has been in an electrically floating state at the precharged potential is discharged to the ground potential level. Then, sense amplifier activating signal .phi.SP is activated, so that P-sense amplifier 27 operates to charge the potential of bit line BL to the operation power supply voltage Vcc level. During rise of the potential of bit line BL, the potential of nonselected word line WLb also rises due to capacitive coupling of parasitic capacitance 26b. When the potential of bit line /BL is discharged to the ground level during the operation of N-sense amplifier 28, the potential of nonselected word line WLb is already at the ground potential level, and, in the case of its capacitive coupling during the N sense amplifier operation, the access transistor of nonselected memory cell MCe is turned off more strongly, which state is not related particularly to "disturb" to be described later, and thus the waveform thereof is not shown.
When the potential of selected word line WLa falls from the high level to the low level upon termination of one memory cycle, the potential of word line WLb lowers through capacitive coupling by parasitic capacitance 25c. At this time, the potential of bit line /BL which has been discharged to the ground potential level by N-sense amplifier 28 lowers through parasitic capacitance 26c.
The above floating up of potential of nonselected word line WLb causes a problem of "disturb" that the quantity of electric charges accumulated in capacitor 23 of nonselected memory cell MCe is changed, and data stored in the memory cell changes, as will be described below in detail.
FIGS. 35A-35C show a manner of the disturb of memory cell data at the time of floating up of the word line potential.
As shown in FIG. 35A, when the potential of nonselected word line WLb rises at the time of rise of the potential of selected word line WLa (at A in FIG. 34), access transistor 22 is weakly turned on in the case where data of the high level (Vcc) is stored in capacitor 23 of the memory cell connected to nonselected word line WLb, so that charges Q flow from capacitor 23 onto bit line /BL. It is not essential that floating up value .DELTA.V1 of the potential of nonselected word line WLb is equal to or greater than the threshold voltage of access transistor 22. Even if the potential of nonselected word line WLb rises up to the threshold voltage level of access transistor 22, charges Q flow from capacitor 23 to bit line /BL, because its subthreshold current increases.
In FIG. 35B, P-sense amplifier 27 operates, the potential of bit line BL rises and its parasitic capacitance 26b raises the potential of nonselected word line WLb. At this time, the potential of bit line /BL is at the ground potential Vss level, and charges Q at the high level (Vcc level) accumulated in capacitor 23 of the memory cell flow onto bit line /BL.
As shown in FIG. 35C, when parasitic capacitance 26c shown in FIG. 33 lowers the potential of bit line /BL to a negative potential -.DELTA.Vb during transition of selected word line WLa to the nonselected state, charges Q of high level data accumulated in capacitor 23 related to nonselected word line WLb flow onto bit line /BL if the potential of nonselected word line WLb is equal to the ground potential Vss or negative potential -.DELTA.Va.
The flow of accumulated charges occurs not only during data reading but also during data writing. More specifically, this occurs when the word line is set to the selected state and when the sense amplifier operates.
In the case where capacitor 23 has stored data at the low level, the source of the access transistor is a node connected to capacitor 23, and the capacitance of capacitor 23 is significantly small as compared with the capacitances of bit lines BL and /BL, so that even a small amount of electric charges flown into capacitor 23 raises the potential of capacitor 23. Whereby, potentials of the gate and source of access transistor 22 becomes equal to each other, and thus flow of the electric charges via the access transistor stops. Therefore, the amount of charges of memory cell capacitor 23 storing data of the low level is increased but does not exceed a limited level.
However, in the case where data of the high level has been stored, electric charges flow from the memory cell capacitor to the corresponding bit line upon each operation of selecting a word line, so that the potential of the memory cell capacitor lowers as shown in FIG. 36. FIG. 36 shows variation in the potential of word line WL(l) in the case where word lines WL(l-1), WL(l+1), WL(1+2) . . . are successively selected. In general, a capacitance value of the memory cell capacitor is determined to have a margin for leak of charges during operation. However, the capacitance value of the memory cell capacitor may decrease due to variation in manufacturing parameters such as thickness of a capacitor insulating film and an area of opposing portions of capacitor electrodes, in which case such a problem occurs that even leak of a small amount of electric charges lowers the electrode potential of the capacitor, resulting in inversion of stored data.
As summing that C represents the capacitance value of memory cell capacitor 23 and Q represents the amount of accumulated charges, the following formula is obtained, where cell plate potential Vcp is equal to Vcc/2. EQU Q=C.multidot.Vcc/2
Assuming that electric charges of a quantity .DELTA.Q leak at a time, variation .DELTA.V of electrode potential of the capacitor can be expressed by the following formula: EQU .DELTA.Q=C.multidot..DELTA.V
Therefore, if the capacitance value C of capacitor 23 decreases, potential variation .DELTA.V increases even if the quantity .DELTA.Q of electric charges flown out therefrom is constant. Therefore, as shown in FIG. 36, the electrode potential of capacitor of a defective cell having a smaller capacitance value lowers to a large extent as compared with an extent of change of the electrode potential of capacitor of a normal memory cell indicated by broken line.
A so-called "disturb" test is one of tests for detecting existence of such a defective cell.
In this disturb test, word lines other than the word line connected to the memory cell of interest are selected predetermined number of times (disturb times), and it is determined whether the memory cell of interest accurately holds data or not. In this disturb test, the disturb test is effected simultaneously on a large number of semiconductor memory devices.
FIG. 37 schematically shows a structure for executing the disturb test. In FIG. 37, a plurality of semiconductor memory devices DR11-DRmn are arranged on a test board TB. FIG. 37 illustrated a state where semiconductor memory devices DR11-DRmn are arrange in m rows and n columns on test board TB. Semiconductor memory devices DR11-DRmn are connected via a signal bus SG. Test board TB is connected to a test unit TA. Test unit TA applies signals onto signal bus SG. During testing, disturb test is effected simultaneously on these semiconductor memory devices DR11-DRmn. Initially in the disturb test, data of the high level is written into semiconductor memory devices DR11-DRmn. Then, test unit TA applies row address strobe signal /RAS and address signals onto signal bus SG, so that semiconductor memory devices DR11-DRmn operate to select the word lines and activate the sense amplifier circuits. By repeating this word line selection predetermined number of times, respective word lines WL connected to the memory cells are influenced by noises, and charges leak from the memory cell capacitors. After the predetermined number of times of operation of selecting the word line and activating the sense amplifier circuits, it is determined whether data stored in semiconductor memory devices DR11-DRmn are of the high level or not. Test unit TA executes this determination.
As the storage capacity of the semiconductor memory device increases, the word lines contained therein increase in number. This results in disadvantageous increase of the time required for the disturb test in which the word lines are successively selected. In order to reduce the test time, such a method may be envisaged that control signal /RAS transmitted from test unit TA in FIG. 37 onto signal bus SG is changed rapidly so as to reduce the time period for which the word line is at the selected state. However, a large number of semiconductor memory devices DR11-DRmn are connected to signal bus SG, and large parasitic capacitances Cp exist at signal bus SG as shown in FIG. 37. Therefore, the interconnection line resistance of signal bus SG and the large parasitic capacitances CP cause signal propagation delay, and required signals cannot be changed fast.
FIGS. 38A and 38B illustrate change in control signal /RAS and an address signal on signal bus SG. FIG. 38A shows ideal signal waveforms on signal bus SG, and FIG. 38B shows signal waveforms on signal bus SG in the conventional disturb test. In the ideal state shown in FIG. 38A, signal /RAS changes with predetermined rising and falling times without being influenced by delay in signal propagation. The address signal requires a set-up time Ts and a hold time Th with reference to signal /RAS. Set-up time Ts is a time required for establishing and maintaining the fixed state prior to falling of signal /RAS. Hold time Th is a time required for maintaining the fixed state of address signal after the falling of signal /RAS.
Meanwhile, in the case where parasitic capacitance Cp of signal bus SG is large, the rising time and falling time of control signal /RAS increase, e.g., to 50 ns (nanoseconds) due to delay in signal propagation on signal bus SG, so that fast change thereof is impossible. In this case, the changing speed of the address signal also decreases. In order to ensure the intended address set-up time Ts, it is necessary to change the address signal at the timing preceding the timing of change of the address signal of the ideal waveform (FIG. 38A). In order to change the address signal while control signal /RAS is at the high level of the inactive state, the period of inactive state of control signal /RAS must be made longer than that of the ideal waveform. This results in increase of the time of one cycle (word line selecting cycle) of the disturb test, so that successive selection of the word lines cannot be performed fast, and thus the disturb test time cannot be reduced.
The above problem that fast and successive selection of the word lines cannot be performed in the test operation arises also in an acceleration test such as a "burn-in" test. In the "burn-in" test, semiconductor memory devices are operated under the conditions of high temperature and high humidity to exclude defective products before marketing by making manifest latent initial failures in components such as a failure in a gate insulating film of an MOS transistor, failure in an interlayer insulating film between interconnections, a failure in interconnections and a failure caused by particles mixed at manufacturing steps. In the acceleration test such as a burn-in test, only operating conditions of the semiconductor memory device are changed, and the semiconductor memory device operates in the same manner as in the normal operation in accordance with control signals applied from an externally arranged test unit. Therefore, the word lines are successively selected also in this acceleration test, so that the test time cannot be reduced. This problem arises also in another test such as a life-time test.
Semiconductor memory devices employs different specification values such as operation conditions for different families. If different design rules are employed, the word line pitch and memory capacitor capacitance take different values, and the degree of floating up of the word line potential and the variation of the potential of the memory capacitor take different values. Therefore, depending on the family member of the semiconductor memory device, word line select cycle period (i.e., period for which the word line is in the selected state) and the number of times of word line selection must be changed. Such change of the test conditions requires change in a program operating the test unit, resulting in such a problem that the test conditions cannot be changed flexibly and easily depending on the family member of the semiconductor memory device to be tested.